Virtex-6 FPGA OverView
Table of Contents
docs
This section provides references to documentation supporting Virtex-6 FPGAs, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm.
- UG534, ML605 Hardware User Guide
- UG535, ML605 Reference Design User Guide
- DS150, Virtex-6 Family Overview
- DS152, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
- UG360, Virtex-6 FPGA Configuration User Guide
- UG361, Virtex-6 FPGA SelectIO Resources User Guide
- UG362, Virtex-6 FPGA User Guide: Clocking Resources
- UG363, Virtex-6 FPGA Memory Resources User Guide
- UG364, Virtex-6 FPGA Configurable Logic Block User Guide
- UG365, Virtex-6 FPGA Packaging and Pinout Specifications
- UG366, Virtex-6 FPGA GTX Transceivers User Guide
- UG369, Virtex-6 FPGA DSP48E1 Slice User Guide
- DS186, Virtex-6 FPGA Memory Interface Solutions Data Sheet
- UG370, Virtex-6 FPGA System Monitor User Guide
- DS643, Multi-Port Memory Controller (MPMC) (v5.02a) Data Sheet
- UG086, Memory Interface Solutions User Guide
- UG138, LogiCORE™ IP Tri-Mode Ethernet MAC v4.3 User Guide
- UG517, LogiCORE™ IP Virtex-6 FPGA Integrated Block User Guide v1.3 for PCI Express
- DS715, Virtex-6 FPGA Integrated Block v1.3 for PCI Express Data Sheet
- Platform Studio EDK
ML605 tutorials and design files are located at http://www.xilinx.com/products/boards/ml605/reference_designs.htm:
Virtex-6 FPGA ML605 Evaluation Kit - 13.4 docs
Notes
UG360 Virtex-6 FPGA Configuration User Guide Notes
- OverView
These configuration pins serve as the interface for a number of different configuration modes:
- Master-Serial configuration mode
- Slave-Serial configuration mode
- Master SelectMAP (parallel) configuration mode (x8 and x16)
- Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)
- JTAG/boundary-scan configuration mode
- Master Serial Peripheral Interface (SPI) flash configuration mode
- Master Byte Peripheral Interface Up or Down (BPI-Up or BPI-Down) flash configuration mode (x8 and x16 only)
The terms Master and Slave refer to the direction of the configuration clock (CCLK):
- In Master configuration modes, the Virtex-6 device drives CCLK from an internal oscillator. To select the desired frequency, BitGen -g ConfigRate option is used. The BitGen section of UG628, Command Line Tools User Guide provides more information.
- In Slave configuration modes, CCLK is an input.
- Chapter 2
Virtex-6 FPGA Configuration Modes
Configuration Mode M[2:0] Bus Width CCLK Direction
Master Serial 000 1 Output
Master SPI 001 1 Output
Master BPI-Up 010 8, 16 Output
Master BPI-Down 011 8, 16 Output
Master SelectMAP 100 8, 16 Output
JTAG 101 1 Input (TCK)
Slave SelectMAP 110 8, 16, 32 Input
Slave Serial 111 1 Input
- Master BPI Configuration Interface
From the Master Byte-wide Peripheral Interface (BPI), the Virtex-6 FPGA can configure itself in BPI-Up (M[2:0]=010) or BPI-Down (M[2:0] = 011) mode.
In BPI modes, the CCLK output is not connected to the BPI flash device. However, the FPGA outputs an address after the rising edge of CCLK, and the data is still sampled on the next rising edge of CCLK. The timing parameters related to BPI use CCLK as a reference.
In the BPI-Up mode, the address starts at 0 and increments by 1 until the DONE pin is asserted.
In the BPI-Down mode, the address start at 26’h3FFFFFF and decrements by 1 until the DONE pin is asserted.
The iMPACT programming software provides the ability to program Top boot parallel NOR flash using an indirect programming method. “Introduction to Indirect Programming – SPI or BPI Flash Memory.” For software flow details, see XAPP973, Indirect Programming of BPI PROMs with Virtex-5 FPGAs.
- Master BPI Configuration Interface